Engineering:Tick–tock model

From HandWiki
Short description: Production model by Intel

Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture.[1] These occurred roughly every year to 18 months.[2] In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture[3] not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.[4] The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake,[5] making a total of four generations at 14 nm.[6]

Roadmap

Pentium 4 / Core roadmap

Pentium 4 / Core roadmap
Change
(step)
Fabri­cation
process
Micro-
architecture
Code names
for step
Intel
Generation
Desktop
Intel
Generation
Xeon
Intel Microcode
shortcut(s)
Desktop/WS[7][8]
Intel Microcode
shortcut(s)
Xeon/Server
Release
date
Processors
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Tick
(new fabrica-
tion process
)
65 nm P6, NetBurst Yonah (P6),
Presler (NetBurst),
Cedar Mill (NetBurst)
N/A 1995-11-1 (P6),
2000-11-20 (NetBurst)
N/A N/A N/A Presler (NetBurst) Cedar Mill (NetBurst) Yonah (P6)
Tock
(new micro-
architecture
)
Core Merom[9] 2006-07-27[10][11] Tigerton Woodcrest
Clovertown
Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[12] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1 N/A NHM[13] N/A 2008-11-17[14] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1 WSM[13] 2010-01-04[15][16] Westmere-EX Westmere-EP N/A Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 2 1 SNB JKT (Jaketown) 2011-01-09[17] (Skipped)[18] Sandy Bridge-EP Gladden Sandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[19] Ivy Bridge 3 2 IVB IVT (Ivytown) 2012-04-29 Ivy Bridge-EX[20] Ivy Bridge-EP[20] Gladden Ivy Bridge Ivy Bridge-E[21] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 4 3 HSW, CRW (Crystal Well)
with Iris Pro[22][23]
HSX 2013-06-02 Haswell-EX Haswell-EP N/A Haswell-DT Haswell-E Haswell-DT[24] Haswell-MB (notebooks)
Haswell-LP (ultrabooks)[24]
Refresh Haswell Refresh,
Devil's Canyon[25]
4 N/A HSW, CRW (Crystal Well)
with Iris Pro[22][23]
N/A 2014-05-11,
2014-06-02
No server version released Devil's Canyon No mobile version
released
Tick (Process) 14 nm[19] Broadwell[26] 5 4 BDW BDX 2014-09-05 Broadwell-EX[27] Broadwell-EP[27] Broadwell-DE Broadwell-DT Broadwell-E Broadwell-DT Broadwell-H
Broadwell-U
Broadwell-Y
Tock (Architecture) Skylake[26] Skylake[26] 6 5 SKL SKX 2015-08-05[28] Skylake-SP Skylake-DE Skylake-DT/H Skylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimization
(Refresh)
[4][29][30][31]
Kaby Lake[32] 7 6 KBL N/A 2017-01-03[33] Only 1P server (Xeon E3) version released Kaby Lake-DT/H
cores: 4 (4/8)
Kaby Lake-X[34] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R[35][36] 8 N/A KBL-R 2017-08-21[36] Only mobile version released Kaby Lake R
Coffee Lake 8, 9[37] E-2xxx CFL 2017-10-05[38] Cascade Lake-SP
Cooper Lake (Q2'20)
Cascade Lake-AP Coffee Lake-DT/H
cores: 6 (12)
Skylake-X Refresh Coffee Lake-S
Coffee Lake-R
Coffee Lake-H
Coffee Lake-U
Coffee Lake-H Refresh
Whiskey Lake,
Amber Lake[39]
8 N/A WHL
AML
2018-08-28[39] Only mobile version released Whiskey Lake-U
Amber Lake-Y
Comet Lake[40] 10 CML 2019-08-21[40] No server version released Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Architecture Cypress Cove[41] Rocket Lake[41] 11 RKL 2021-03-30[42] N/A Rocket Lake-S N/A
Process 10 nm Palm Cove Cannon Lake 8 CNL 2018-05-16[43] Only mobile version released Cannon Lake-U
Architecture Sunny Cove Ice Lake[44] 10 3 ICL 2019-08-01[45] Ice Lake-SP (1H21)[46] N/A Ice Lake-U
Ice Lake-Y
Optimization[31] Willow Cove Tiger Lake[31] 11 N/A TGL 2020-09-02[47] Only mobile version released Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Architecture Intel 7 Golden Cove Alder Lake 12 ADL 2021-11-04 No server / WS version released Alder Lake-S Alder Lake-HX
Alder Lake-H
Alder Lake-P
Alder Lake-U
Sapphire Rapids[48] N/A 4 N/A SPR 2023-01-10 Sapphire Rapids-SP TBA Only server / WS version released
Optimization Raptor Cove Raptor Lake 13 N/A RPL N/A 2022-10-20 No server / WS version released Raptor Lake-S Raptor Lake-HX
Raptor Lake-H
Raptor Lake-P
Raptor Lake-U
Emerald Rapids N/A 5 N/A EMR 2023 Emerald Rapids-SP TBA Only server / WS version released
Tick Intel 4[49] Redwood Cove Meteor Lake[50] 14 N/A MTL N/A 2023-12-14 No server / WS version released TBA
Tick Intel 3 Granite Rapids[51] N/A 6 N/A GNR 2024 Granite Rapids-SP TBA Only server / WS version released
Tick Intel 20A Lion Cove Arrow Lake[52] 15 N/A ARL N/A 2024 No server / WS version released TBA
Tick Intel 18A TBA Lunar Lake 16 N/A LNL N/A 2025 No server / WS version released TBA
Change
(step)
Fabri­cation
process
Micro-
architecture
Code names
for step
Intel
Generation
Desktop
Intel
Generation
Xeon
Intel Microcode
shortcut(s)
Desktop/WS[7][8]
Intel Microcode
shortcut(s)
Xeon/Server
Release
date
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Processors

Atom roadmap

With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process did not allow to do this. In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom but it allows us to understand what changes happened in each generation.

Atom roadmap[53]
Change Fabri­cation
process
Micro-
architecture

(Abbr.)[13]
Code names
for step
Release
date
Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server CE
Process / Architecture 45 nm Bonnell (BNL) Bonnell 2008 Silverthorne N/A Diamondville N/A N/A N/A
Optimization Bonnell 2010 Lincroft Pineview Tunnel Creek
Stellarton
N/A Sodaville
Groveland
Process 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) N/A Centerton & Briarwood Berryville
Process / Architecture 22 nm Silvermont (SLM) Silvermont 2013 Merrifield (Tangier)[54] & Moorefield (Anniedale)[55] & Slayton Bay Trail-T
(Valleyview)
Bay Trail-M
(Valleyview)
Bay Trail-D
(Valleyview)
Bay Trail-I
(Valleyview)
Avoton
Rangeley
Unknown
Process 14 nm[53] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[56] Braswell[57] Denverton
Cancelled
Unknown
Architecture Goldmont[58]
(GLM)
Goldmont 2016 Broxton Cancelled Broxton Cancelled
Apollo Lake
Apollo Lake Apollo Lake Unknown Denverton Unknown
Architecture Goldmont Plus
(GLM+, GLP)
Goldmont Plus 2017 Unknown Gemini Lake Gemini Lake Gemini Lake Unknown Unknown Unknown
Optimization Goldmont Plus 2019 Unknown Gemini Lake Refresh Gemini Lake Refresh Gemini Lake Refresh Unknown Unknown Unknown
Process / Architecture 10 nm Tremont Tremont 2020 Unknown Jasper Lake Jasper Lake Jasper Lake Elkhart Lake Snow Ridge Unknown
Architecture Intel 7 Gracemont Gracemont 2021 Unknown Unknown Alder Lake & Raptor Lake (hybrid) Unknown Unknown
Process / Architecture Intel 4 Crestmont Crestmont 2023 Unknown Unknown Meteor Lake[59] (hybrid) Sierra Forest-AP Unknown

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL;[13] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology.[60] In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued.[61] However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.

Both

See also

References

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  2. "Intel tick–tock model". Intel Corporation. http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html. "A yearly product cadence moves the industry forward in a predictable fashion that can be planned in advance." 
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  7. 7.0 7.1 Intel Releases Linux CPU Microcodes To fix Meltdown & Spectre Bugs by Lawrence Abrams on January 11, 2018
  8. 8.0 8.1 Linux* Processor Microcode Data File Version 20180312 on 3/12/2018
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External links

fr:Intel#Stratégies tic-tac et processus-architecture-optimisation