Engineering:3 nm process

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Short description: Semiconductor manufacturing processes with a 3 nm GAAFET/FinFET technology node

In semiconductor manufacturing, the "3 nm" process is the next die shrink after the "5 nm" MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its "3 nm" gate all around (GAA) process, named "3GAA", in mid-2022.[1][2] On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its "3 nm" semiconductor node ("N3") is under way with good yields.[3] An enhanced "3 nm" chip process called "N3E" may have started production in 2023.[4] American manufacturer Intel planned to start 3 nm production in 2023.[5][6][7]

The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "3 nm" node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[8]

Samsung's "3 nm" process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's "3 nm" process still uses FinFET (fin field-effect transistor) technology,[9] despite TSMC developing GAAFET transistors.[10] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[11] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[12]


Node name Actual gate pitch Actual metal pitch Year
"5 nm" 51 nm 30 nm 2020
"3 nm" 48 nm 24 nm 2022
"2 nm" 45 nm 20 nm 2024?

"3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a "3 nm" node. Typically the chip manufacturer refers to its own previous process node (in this case the "5 nm" node) for comparison. For example, TSMC has stated that its "3 nm" FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous "5 nm" FinFET chips.[15][16] On the other hand, Samsung has stated that its "3 nm" process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous "5 nm" process.[17] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[18]

History

Research and technology demos

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[19][20] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[21][22]

Commercialization history

In late 2016, TSMC announced plans to construct a "5 nm"–"3 nm" node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.[23]

In 2017, TSMC announced it was to begin construction of the "3 nm" semiconductor fabrication plant at the Tainan Science Park in Taiwan.[24] TSMC plans to start volume production of the "3 nm" process node in 2023.[25][26][27][28][29]

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out "3 nm" test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[30]

In early 2019, Samsung presented plans to manufacture "3 nm" GAAFET (gate-all-around field-effect transistors) at the "3 nm" node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with "7 nm".[31][32][33] Samsung's semiconductor roadmap also included products at "8", "7", "6", "5", and "4 nm" 'nodes'.[34][35]

In December 2019, Intel announced plans for "3 nm" production in 2025.[36]

In January 2020, Samsung announced the production of the world's first "3 nm" GAAFET process prototype, and said that it is targeting mass production in 2021.[37]

In August 2020, TSMC announced details of its "N3" process, which is new rather than being an improvement over its "N5" process.[38] Compared with the "N5" process, the "N3" process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC was planning volume production in the second half of 2022.[39]Template:And then what

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process, the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.[5]Template:And then what

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers’ first "3 nm"-based chip designs in the first half of 2022, while its second generation of "3 nm" is expected in 2023.[40]Template:And then what

In June 2022, at TSMC Technology Symposium, the company shared details of its "N3E" process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10-15% higher performance at iso power or 30-35% lower power at iso performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of "3 nm" process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.[41][42][43]

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using "3 nm" process technology with GAA architecture.[1][44] According to industry sources, Qualcomm has reserved some of "3 nm" production capacity from Samsung.[45]

On 25 July 2022, Samsung celebrated the first shipment of "3 nm" Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi.[46][47][48][49] It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density,[50] 23% higher performance or 45% lower power draw compared to an unspecified "5 nm" process technology.[51] Goals for the second-generation "3 nm" process technology include up to 35% higher transistor density,[50] further reduction of power draw by up to 50% or higher performance by 30%.[51][52][50]

On 29 December 2022, TSMC announced that volume production using its "3 nm" process technology N3 is under way with good yields.[3] The company plans to start volume manufacturing using refined "3 nm" process technology called N3E in the second half of 2023.[53]

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their "3 nm" process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm² for N3 and 0.021 μm² for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2-2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allows to intermix cells with different number of fins in a single chip.[54][55][56][57]

Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's "3 nm" processes offered only incremental improvements, because limits have been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there will be no more room left for improvement of FinFET-based process technologies.[58]

In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P will offer 5% higher speed or 5%–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X will offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P is scheduled to enter volume production in the second half of 2024, and N3X will follow in 2025.[59]

In July 2023, semiconductor industry research firm TechInsights said it has found that Samsung's "3 nm" GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT.[60]

On 7 September 2023, MediaTek and TSMC announced that MediaTek have developed their first "3 nm" chip, volume production is expected to commence in 2024.[61]

On 12 September 2023, Apple announced the iPhone 15 Pro and iPhone 15 Pro Max would feature a "3 nm" chip, the A17 Pro.[62] One month later, on 30 October 2023, the "3 nm" process made it into the M3 chip family (M3, M3 Pro and M3 Max) which powers the MacBook Pro and iMac.[63]

"3 nm" process nodes

Samsung[40][64][65][66] TSMC[67] Intel[5]
Process name 3GAE 3GAP 3GAP+ N3 N3E N3S N3P N3X 3
Transistor type MBCFET FinFET
Transistor density (MTr/mm2) 150[65] 195[65] Unknown 197[43] (theoretical)

183 (A17 Pro)[68]

215.6[69] Unknown 224.2[70] 224.2[70] Unknown
SRAM bit-cell size (μm2) Unknown Unknown Unknown 0.0199[56] 0.021[56] Unknown Unknown Unknown Unknown
Transistor gate pitch (nm) 40 Unknown Unknown 45[56] 48[69] Unknown Unknown Unknown Unknown
Interconnect pitch (nm) 32 Unknown Unknown Unknown 23[56] Unknown Unknown Unknown Unknown
Release status 2022 risk production[40]
2022 production[1]
2022 shipping[2] 		2024 production 2025 production 2021 risk production
2022 H2 volume production[67][3]
2023 H1 shipping for revenue[71] 		2023 H2 production[67] 2024 H1 production[43] 2024 H2 production[59] 2025 production[59] 2023 H2 product manufacturing[5]
2024 fabbing of Xeons[72]

References

  1. ↑ 1.0 1.1 1.2 "Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture" (Press release). Samsung. Archived from the original on 30 June 2022. Retrieved 30 June 2022.
  2. ↑ 2.0 2.1 "History is made! Samsung beats out TSMC and starts shipping 3nm GAA chipsets". 25 July 2022. https://www.phonearena.com/news/samsung-first-to-ship-3nm-gaa-chips_id141505. 
  3. ↑ 3.0 3.1 3.2 "TSMC Kicks Off 3nm Production: A Long Node to Power Leading Chips". 29 December 2022. https://www.tomshardware.com/news/tsmc-kicks-off-3nm-production. 
  4. ↑ Ramish Zafar (4 March 2022). "TSMC Exceeds 3nm Yield Expectations & Production Can Start Sooner Than Planned". https://wccftech.com/tsmc-exceeds-3nm-yield-expectations-production-can-start-sooner-than-planned/. 
  5. ↑ 5.0 5.1 5.2 5.3 Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros. 
  6. ↑ Gartenberg, Chaim (26 July 2021). "Intel has a new architecture roadmap and a plan to retake its chipmaking crown in 2025". The Verge. https://www.theverge.com/2021/7/26/22594074/intel-acclerated-new-architecture-roadmap-naming-7nm-2025. 
  7. ↑ "Intel Technology Roadmaps and Milestones" (in en). https://www.intel.com/content/www/us/en/newsroom/news/intel-technology-roadmaps-milestones.html#gs.tuhd2s. 
  8. ↑ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 7, https://irds.ieee.org/editions/2021/more-moore, retrieved 7 August 2022 
  9. ↑ Cutress, Dr Ian. "Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm". https://www.anandtech.com/show/16041/where-are-my-gaafets-tsmc-to-stay-with-finfet-for-3nm. 
  10. ↑ "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond – ExtremeTech". https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond. 
  11. ↑ "Samsung at foundry event talks about 3nm, MBCFET developments". https://techxplore.com/news/2019-05-samsung-foundry-event-3nm-mbcfet.html. 
  12. ↑ Patrick Moorhead (26 July 2021). "Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies". https://www.forbes.com/sites/patrickmoorhead/2021/07/26/intel-updates-idm-20-strategy-with-new-node-naming-and-technologies/?sh=59b7592729d5. 
  13. ↑ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers. 
  14. ↑ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum (IEEE). https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors. Retrieved 20 April 2021. 
  15. ↑ Jason Cross (25 August 2020). "TSMC details its future 5nm and 3nm manufacturing processes—here's what it means for Apple silicon". Macworld. https://www.macworld.com/article/234529/tsmc-details-its-future-5nm-and-3nm-manufacturing-processesheres-what-it-means-for-apple-silicon.html. 
  16. ↑ Anton Shilov (31 August 2020). "The future of leading-edge chips according to TSMC: 5nm, 4nm, 3nm and beyond". https://www.techradar.com/news/the-future-of-leading-edge-chips-according-to-tsmc-5nm-4nm-3nm-and-beyond. 
  17. ↑ "Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture". 30 June 2022. https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture. 
  18. ↑ Chen, Frederick (17 July 2022). "EUV's Pupil Fill and Resist Limitations at 3nm". https://www.linkedin.com/pulse/euvs-pupil-fill-resist-limitations-3nm-frederick-chen. 
  19. ↑ Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010) (in en). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083. https://books.google.com/books?id=IljcLHKwM3EC&pg=PA17. Retrieved 11 October 2019. 
  20. ↑ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K. et al. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. 
  21. ↑ "Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, http://www.highbeam.com/doc/1G1-145838158.html 
  22. ↑ Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan et al. (June 2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". pp. 58–59. doi:10.1109/VLSIT.2006.1705215. ISBN 978-1-4244-0005-8. 
  23. ↑ Patterson, Alan (12 December 2016), TSMC Plans New Fab for 3nm, https://www.eetimes.com/tsmc-plans-new-fab-for-3nm/, retrieved 22 July 2023 
  24. ↑ Patterson, Alan (2 October 2017), TSMC Aims to Build World's First 3-nm Fab, https://www.eetimes.com/tsmc-aims-to-build-worlds-first-3-nm-fab/, retrieved 22 July 2023 
  25. ↑ Zafar, Ramish (15 May 2019). "TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report". https://wccftech.com/tsmc-2nm-research-taiwan/. 
  26. ↑ "TSMC to start production on 5nm in second half of 2020, 3nm in 2022". 8 December 2019. https://www.techspot.com/news/83080-tsmc-start-production-5nm-second-half-2020-3nm.html. 
  27. ↑ Armasu 2019-12-06T20:26:59Z, Lucian (6 December 2019). "Report: TSMC To Start 3nm Volume Production In 2022". https://www.tomshardware.com/news/report-tsmc-to-start-3nm-volume-production-in-2022. 
  28. ↑ "TSMC 3nm process fab starts construction - mass production in 2023". 25 October 2019. https://www.gizchina.com/2019/10/25/tsmc-3nm-process-fab-starts-construction-mass-production-in-2023/. 
  29. ↑ Friedman, Alan (27 October 2019). "TSMC starts constructing facilities to turn out 3nm chips by 2023". https://www.phonearena.com/news/TSMC-starts-building-facilities-to-manufacture-3nm-chips_id119977. 
  30. ↑ "Imec and Cadence Tape Out Industry's First 3nm Test Chip". Cadence (Press release). 28 February 2018. Retrieved 18 April 2019.
  31. ↑ "Samsung Unveils 3nm Gate-All-Around Design Tools - ExtremeTech". https://www.extremetech.com/extreme/291507-samsung-unveils-3nm-gate-all-around-design-tools. 
  32. ↑ Armasu, Lucian (11 January 2019), Samsung Plans Mass Production of 3nm GAAFET Chips in 2021, https://www.elinfor.com/news/samsung-3nm-process-is-one-year-ahead-of-tsmc-in-gaa-and-three-years-ahead-of-intel-p-11201, retrieved 6 December 2019 
  33. ↑ Samsung: 3nm process is one year ahead of TSMC in GAA and three years ahead of Intel, 6 August 2019, https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html, retrieved 18 April 2019 
  34. ↑ Armasu, Lucian (25 May 2017), Samsung Reveals 4nm Process Generation, Full Foundry Roadmap, https://www.tomshardware.com/news/samsung-4nm-foundry-roadmap-revealed,34515.html, retrieved 18 April 2019 
  35. ↑ Cutress, Ian. "Samsung Announces 3nm GAA MBCFET PDK, Version 0.1". https://www.anandtech.com/show/14333/samsung-announces-3nm-gaa-mbcfet-pdk-version-01. 
  36. ↑ Cutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029. 
  37. ↑ Broekhuijsen 2020-01-03T16:28:57Z, Niels (3 January 2020). "Samsung Prototypes First Ever 3nm GAAFET Semiconductor" (in en). https://www.tomshardware.com/news/samsung-prototypes-first-ever-3nm-gaafet-semiconductor. 
  38. ↑ Shilov, Anton. "TSMC: 3nm EUV Development Progress Going Well, Early Customers Engaged". https://www.anandtech.com/show/14666/tsmc-3nm-euv-development-progress-going-well-early-customers-engaged. 
  39. ↑ "TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming". 22 April 2022. https://www.anandtech.com/print/17356/tsmc-roadmap-update-n3e-in-2024-n2-in-2026-major-changes-incoming. 
  40. ↑ 40.0 40.1 40.2 "Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices" (Press release). Samsung. 7 October 2021. Archived from the original on 8 April 2022. Retrieved 23 March 2022.
  41. ↑ "TSMC Technology Symposium Review". 22 June 2022. https://semiwiki.com/semiconductor-manufacturers/tsmc/314415-tsmc-2022-technology-symposium-review-process-technology-development/. 
  42. ↑ "TSMC Readies Five 3nm Process Technologies, Adds FinFlex For Design Flexibility". 16 June 2022. https://www.anandtech.com/print/17452/tsmc-readies-five-3nm-process-technologies-with-finflex. 
  43. ↑ 43.0 43.1 43.2 "N3E Replaces N3; Comes In Many Flavors". 4 September 2022. https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/. 
  44. ↑ "Samsung Starts 3nm Production: The Gate-All-Around (GAAFET) Era Begins". 30 June 2022. https://www.anandtech.com/print/17474/samsung-starts-3nm-production-the-gaafet-era-begins. 
  45. ↑ "Samsung Electronics begins 'trial production' of 3-nano foundry...The first customer is a Chinese ASIC company". 28 June 2022. https://www-thelec-kr.translate.goog/news/articleView.html?idxno=17300&_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=en&_x_tr_pto=wapp. 
  46. ↑ "Samsung's 3nm trial production run this week to make Bitcoin miner chips". 28 June 2022. https://www.sammobile.com/news/samsung-3nm-trial-production-run-this-week-make-bitcoin-miner-chips/. 
  47. ↑ "Samsung ships its first set of 3nm chips, marking an important milestone". 25 July 2022. https://www.sammobile.com/news/samsung-3nm-chips-shipped-important-milestone/. 
  48. ↑ "Samsung celebrates the first shipment of 3nm Gate-All-Around chips". 25 July 2022. https://www.gsmarena.com/samsung_celebrates_the_first_shipment_of_3nm_gateallaround_chips-news-55179.php. 
  49. ↑ "Samsung Electronics Holds 3 Nano Foundry Mass Production Shipment Ceremony" (Press release). Samsung. 25 July 2022.
  50. ↑ 50.0 50.1 50.2 "Samsung holds ceremony to mark 1st shipment of most advanced 3nm chips". 25 July 2022. https://m-en.yna.co.kr/view/AEN20220725002400320. 
  51. ↑ 51.0 51.1 "Samsung Begins Chip Production Using 3nm Process Technology with GAA Architecture". 29 June 2022. https://www.businesswire.com/news/home/20220629005894/en. 
  52. ↑ "Samsung starts shipping world's first 3nm chips". 25 July 2022. https://m.koreaherald.com/view.php?ud=20220725000623. 
  53. ↑ "TSMC's 3nm Journey: Slow Ramp, Huge Investments, Big Future". 17 January 2023. https://www.anandtech.com/print/18727/tsmcs-3nm-journey-slow-ramp-huge-investments-big-future. 
  54. ↑ Patel, Dylan (21 December 2022). "TSMC's 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed". https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-even. 
  55. ↑ Patel, Dylan (2 February 2023). "IEDM 2022 Round-Up". https://www.semianalysis.com/p/iedm2022p1. 
  56. ↑ 56.0 56.1 56.2 56.3 56.4 Jones, Scotten (1 February 2023). "IEDM 2022 – TSMC 3nm". https://semiwiki.com/semiconductor-manufacturers/tsmc/322688-iedm-2022-tsmc-3nm/. 
  57. ↑ Schor, David (14 December 2022). "IEDM 2022: Did We Just Witness The Death Of SRAM?". https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/. 
  58. ↑ James, Dick. "TSMC Reveals 3nm Process Details". https://www.techinsights.com/blog/tsmc-reveals-3nm-process-details. 
  59. ↑ 59.0 59.1 59.2 "TSMC Details 3nm Evolution: N3E On Schedule, N3P and N3X To Deliver 5% Performance Gains". 26 April 2023. https://www.anandtech.com/print/18833/tsmc-details-3nm-evolution-n3e-on-schedule-n3p-n3x-deliver-five-percent-gains. 
  60. ↑ "TechInsights: Samsung's 3nm GAA process identified in a crypto-mining ASIC designed by China startup MicroBT" (in en). 18 July 2023. https://www.digitimes.com/news/a20230718VL203/samsung-china-3nm-asic.html. 
  61. ↑ Neowin ·, Omer Dursun (7 September 2023). "MediaTek develops its first 3nm chip using TSMC process, coming in 2024" (in en). https://www.neowin.net/news/mediatek-develops-its-first-3nm-chip-using-tsmc-process-coming-in-2024/. 
  62. ↑ "iPhone 15 Pro and iPhone 15 Pro Max" (in en-US). https://www.apple.com/iphone-15-pro/. 
  63. ↑ "Apple unveils M3, M3 Pro, and M3 Max, the most advanced chips for a personal computer" (in en-US). https://www.apple.com/newsroom/2023/10/apple-unveils-m3-m3-pro-and-m3-max-the-most-advanced-chips-for-a-personal-computer/. 
  64. ↑ "Can TSMC maintain their process technology lead". 29 April 2020. https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/. 
  65. ↑ 65.0 65.1 65.2 "Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". 5 July 2022. https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/. 
  66. ↑ "Samsung Foundry Vows to Surpass TSMC within Five Years". https://www.anandtech.com/show/18854/-samsung-foundry-vows-to-surpass-tsmc-within-five-years. 
  67. ↑ 67.0 67.1 67.2 "TSMC 3nm" (in en-us). 15 April 2022. https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm. 
  68. ↑ "A17 Pro Overall Analysis" (in en). https://twitter.com/Tech_Reve/status/1706472603752575103. 
  69. ↑ 69.0 69.1 "TSMC N3, and Challenges Ahead". 27 May 2023. https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/. 
  70. ↑ 70.0 70.1 "TSMC Details 3nm Evolution: N3E On Schedule, N3P and N3X To Deliver 5% Performance Gains". 26 April 2023. https://www.anandtech.com/print/18833/tsmc-details-3nm-evolution-n3e-on-schedule-n3p-n3x-deliver-five-percent-gains. 
  71. ↑ "TSMC Q2 2022 Earnings Call". 14 July 2022. https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2022-07/185efaefea866a5e944499cda9eeecc65315449c/TSMC%202Q22%20Transcript.pdf. 
  72. ↑ Cutress, Dr Ian (17 February 2022). "Intel Discloses Multi-Generation Xeon Scalable Roadmap: New E-Core Only Xeons in 2024". https://www.anandtech.com/show/17259/intel-discloses-multigeneration-xeon-scalable-roadmap-new-ecore-only-xeons-in-2024. 

Further reading

External links


Preceded by
5 nm (FinFET) 		MOSFET semiconductor device fabrication process Succeeded by
2 nm (GAAFET)



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