Engineering:Process-Architecture-Optimization model
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Revision as of 21:45, 16 December 2020 by imported>Scavis2 (over-write)
Process–architecture-optimization is a processor development model adopted in 2016 by Intel. Under this three-phase model, every die shrink is followed by a microarchitecture change and then by an optimization. It replaced the two-phase Tick–tock model, adopted by Intel in 2006, because according to Intel the previous model was [and still is] no longer sustainable.[1][2][3][4]
| Scaling | Process | Architecture | Optimizations |
|---|---|---|---|
| 14 nm | Broadwell | Skylake | Kaby Lake, Coffee Lake, Comet Lake, Rocket Lake Mobile only: Amber Lake, Whiskey Lake Server only: Cascade Lake, Cooper Lake |
| 10 nm | Cannon Lake (mobile only) |
Ice Lake (mobile + server) |
Tiger Lake |
References
- ↑ Cutress, Ian. "Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’". https://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization.
- ↑ eTeknix.com (23 March 2016). "Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix". https://www.eteknix.com/intel-ditches-tick-tock-for-process-architecture-optimization/.
- ↑ "Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews". 23 March 2016. http://www.legitreviews.com/intel-tick-tock-processor-model-replaced-process-architecture-optimization_180140.
- ↑ "Intel 7th Gen Core: Process Architecture Optimization". 30 August 2016. http://www.tomshardware.com/reviews/intel-7th-gen-core-kaby-lake-preview,4728-6.html.
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